1. Field of the Invention
The present invention relates to a nonvolatile memory device, and more particularly, to a method for fabricating a nonvolatile memory device, which decreases power consumption and prevents contamination of an insulating layer.
2. Discussion of the Related Art
Nonvolatile memory devices are advantageous in that there is no loss of data even with power supply interruption, which has led to their widespread use for data storage of computer BIOS chips, set-top boxes, printers, network servers, digital cameras, and mobile phones. Among nonvolatile memory devices, an electrically erasable programmable read-only memory (EEPROM) device enables data erase operations from individual memory cells or by sectors. A cell transistor of an EEPROM device is programmed by increasing the transistor's threshold voltage by generating channel hot electrons on the drain side, which are then stored in a floating gate, and is erased by lowering the threshold voltage by generating a high voltage potential between the floating gate and the source/substrate to thereby discharge the stored channel hot electrons.
Meanwhile, flash memory is a specific form of nonvolatile memory by which data bits are stored in units of memory or memory cells. A grouping of memory cells can be termed a word, a grouping of words can be termed a page, and a grouping of pages can be termed a sector. Data can be accessed for reading and programming by word or page, while an entire sector is commonly accessed for erasing, as in a “flash.”
FIGS. 1A and 1B illustrate a process for fabricating a flash memory device according to the related art, which has a stacked gate structure comprising a floating gate and a control gate. The floating gate stores electrical charges for the gate, and the control gate receives a drive voltage.
Referring to FIG. 1A, a tunneling oxide layer 11a is formed on a predetermined portion of a semiconductor substrate 11, and a stacked gate 12 is formed on the tunneling oxide layer by a series of deposition steps to form layers of a stacked gate structure. The stacked gate 12 comprises a polysilicon layer for the formation of a floating gate 12a, a gate insulating layer 12b having an oxide-nitride-oxide structure, and a polysilicon layer for the formation of a control gate 12c, which are sequentially formed on the tunneling oxide layer 11a. The polysilicon layer for floating gate formation has a thickness of 800˜1200 Å formed by low-pressure chemical mechanical deposition, and the polysilicon layer for control gate formation has a thickness of 2000˜2200 Å, also formed by low-pressure chemical mechanical deposition.
Subsequently, a photolithography process is used to form the stacked gate 12 structure, comprised of the control gate 12c, the gate insulating layer 12b, and the floating gate 12a, by etching the structure obtained through previous deposition steps. That is, the photolithography process is used to remove selectively (i.e., etch) portions of the polysilicon layer for control gate formation, the gate insulating layer 12b, and the polysilicon layer for floating gate formation, thereby forming the stacked gate 12. Liner layers (oxide sidewalls) 13 are then formed on lateral sides of the stacked structure, that is, on each of the control gate 12c, the gate insulating layer 12b, and the floating gate 12a. 
Referring to FIG. 1B, insulating sidewalls 14 are formed outwardly beside the liner layers 13. Then, impurity ions are implanted using the stacked gate 12 and the insulating sidewalls 14 as a mask, thereby forming source/drain regions 15 and 16. Subsequently, a silicide layer 17 is formed on exposed surfaces of the source/drain regions 15 and 16 and the control gate 12c. An insulating interlayer 19 is formed on the entire surface of the resulting structure, and a plurality of contact holes is formed in the insulating layer to expose the silicide layer 17 above the source/drain regions 15 and 16 and the control gate 12c. A plurality of plugs 18 is formed by filling the contact holes.
In the above process for fabricating a flash memory device according to the related art, the etching of the photolithography process to form the stacked gate structure includes two steps, namely, wet-etching and dry-etching, which is a complex procedure. This two-step process is performed to minimize plasma damage during photolithography. The gate insulating layer may nevertheless become contaminated as a result of plasma damage or due to the multi-step etching conditions themselves.
To program the above flash memory device according to the related art, a programming voltage is applied to the control gate 12c through a word line and to the drain 16 through a bit line. Thus, electrons of the drain 16 are injected toward the floating gate 12a through the tunneling oxide layer 11a by way of a hot-carrier method. In erasing data, an erasing voltage is applied to the source 15 through a source line. Thus, electrons injected to the floating gate 12a are discharged to the channel through the tunneling oxide layer 11a. 
The above operation is achieved in accordance with a coupling among elements of the stacked gate, specifically, between interfaces of the control gate and the floating gate and between interfaces of the floating gate and the drain, and the coupling ratio should be maximized to decrease power consumption. Therefore, an improvement of the coupling ratio is needed to decrease power consumption of the device, so that low-power flash memory devices can be provided for mobile products requiring low power consumption.